1. Technical Field
The present disclosure generally relates to verification techniques for logic design and in particular to techniques for performing abstraction of logic design using invariants generated over the logic design.
2. Description of the Related Art
Automated property checking techniques hold considerable promise to mitigate what has become one of the most important problems facing the semiconductor industry today: the “verification crisis”. Through the advent of numerous advanced proof, falsification, abstraction and reduction techniques, formal property checking has scaled to the necessary level to address many practical industrial applications, and has become an essential CAD technology. However, many problems remain beyond the capacity of current property checking algorithms, thus continued advances are of critical importance.